The inter-integrated-circuit (I2C) bus is a well-known standard for inter-integrated-circuit communications.
FIG. 1 shows signals from one example of a communication carried out over an I2C bus.
The I2C bus comprises two channels, an SDA serial data channel and an SCL serial clock channel, which transmit information between the devices connected to the I2C bus.
The SCL clock channel is a unidirectional line which transmits a clock signal SCL generated by a master device.
The SDA data channel is a bidirectional line which transmits SDA data signals to be communicated over the I2C bus.
The digital clock signal SCL and data signal SDA are composed of voltage signals that can have a HIGH level or a LOW level.
During a transmission of data, the signal on the SDA line must be stable during the HIGH period of the clock signal. The HIGH or LOW state of the data line SDA can only change when the clock signal on the SCL line is LOW. Generally, the HIGH and LOW levels of the data signal SDA respectively represent the logical values “1” and “0.”
All the transactions begin with a start condition “START” S or repeated start condition Sr and finish with an end condition “STOP” P. A start condition S/Sr is defined by a falling edge (i.e., a HIGH to LOW transition) on the SDA line while the state on the SCL line is HIGH. An end condition P is defined by a rising edge (i.e., a LOW to HIGH transition) on the SDA line while the state of the SCL line is HIGH.
The I2C specification (reference may be made to the document UM10204 version 6.0 of Apr. 4, 2014) recommends the application of a low-pass filter on the incoming data signals SDA and clock signals SCL, in order to eliminate spurious pulses of width tSP less than, for example, 200 ns, preferably less than 50 ns.
The I2C specification also recommends the compliance with a set-up time tSU and a hold time tHD on the transitions of the data signal SDA, with respect to the transitions of the clock signal SCL, in such a manner as to keep the transitions of the data signal SDA away from the transitions of the clock signal SCL.
This avoids, for example, a transition of the signal SDA close to a transition of the signal SCL generating a spurious start or end condition.
Thus, there exist minimum durations to comply with between the transitions of the data signal SDA and the transitions of the clock signal SCL. In particular, a start condition set-up time tSU;STA between a rising edge of the signal SCL and the start condition falling edge of the signal SDA; a start condition hold time tHD;STA between the start condition falling edge of the signal SDA and the respective falling edge of the signal SCL; a data set-up time tSU;DAT between a transition of the signal SDA and the rising edge of the signal SCL; a data hold time tHD;DAT between a falling edge of the signal SCL and a falling edge of the signal SDA; and an end condition set-up time tSU;STO between a rising edge of the signal SCL and the end condition rising edge of the signal SDA.
The values of these durations depend notably on the communication frequency established over the I2C bus.
Thus, when received, filters are implemented on the incoming signals SDA and SCL in order to only consider their transitions in accordance with the specified set-up time and hold time.
In general, these filters on the incoming signals SDA and SCL are implemented with RC filter circuits of the first order.
Typically, the elimination of the spurious positive and negative pulses on each of the two signals uses four RC filter circuits. The verification of the compliance with the set-up time and with the hold time typically uses three RC filter circuits. As a consequence, seven RC filter circuits are typically implemented for the processing of the incoming data signal SDA and of the incoming clock signal SCL.
This type of conventional configuration has the drawback of being very bulky, notably owing to the resistors of the RC filter circuits, of the order of 100 kΩ, which must be formed in width for reasons of stability of characteristics from one fabrication to another.
The developments of fabrication technologies do not allow the size of the resistive elements to be significantly reduced.
As a consequence, the share of the RC filters within the overall surface of the integrated circuits is increasing over time, and can currently, for example, exceed 5% of the surface area of silicon in a 16 Kbit EEPROM memory.
Each RC filter circuit consumes a current specific to it, due to the successive charging and discharging of the capacitor of the filter, through the resistor of the filter. The conventional configurations thus consume a non-negligible amount of current.
Furthermore, in the conventional configurations, the filtering properties of the various RC filter circuits may be subject to relative variations between them, notably owing to the fabrication tolerances and process variations, and this can falsify the reading of the conditions to be detected.
There accordingly exists a need to overcome the various drawbacks of the conventional configurations.